1. Field of the Invention
This invention relates to a method of analyzing and optimizing design of integrated circuit (IC) designs. In particular, the present invention relates to locating constant pins in combinational circuits for the purpose of optimizing such circuits.
2. Description of the Related Art
An integrated circuit chip (hereafter referred to as an xe2x80x9cICxe2x80x9d or a xe2x80x9cchipxe2x80x9d) comprises cells and connections between the cells formed on a surface of a semiconductor substrate. The IC may include a large number of cells and require complex connections between the cells.
A cell is a group of one or more circuit elements such as transistors, capacitors, and other basic circuit elements grouped to perform a function. Each of the cells of an IC may have one or more pins, each of which, in turn, may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip.
A net is a set of two or more pins which must be connected, thus connecting the logic circuits having the pins. Because a typical chip has thousands, tens of thousands, or hundreds of thousands of pins, that must be connected in various combinations, the chip also includes definitions of thousands, tens of thousands, or hundreds of thousands of nets, or sets of pins. The number of the nets for a chip is typically in the same order as the order of the number of cells on that chip. Commonly, a majority of the nets include only two pins to be connected; however, many nets comprise three or more pins.
The binary 0 and 1 states are naturally related to true and false logic variables. Accordingly, Boolean algebra is very useful in the design of electronic logic circuits. A useful way of displaying the results of a Boolean operation is with a truth table.
Electronic circuits that combine digital signals according to Boolean algebra are referred to as xe2x80x9clogic gates.xe2x80x9d Commonly used logic circuits are grouped into families. Such families include, for example, resistor-transistor logic (RTL), diode-transistor logic (DTL), transistor-transistor logic (TTL), N-channel metal-oxide silicon (NMOS), complementary metal-oxide silicon (CMOS) and emitter-coupled logic (ECL). Each family has is advantages and disadvantages. ECL is very fast, for example. MOS features very low power consumption and is therefore often used in VLSI technology.
Given the complexity and size of combinational circuits, it behooves one to simplify the designs of such circuits in order to reduce costs and chip size. In combinational circuit designs there may be cell pins that realize a constant function (i.e., either 1 or 0). The present invention involves a new and novel method and apparatus for detecting such constants in combinational circuits and for simplifying the circuits thereby.
The binary 0 and 1 states are naturally related to true and false logic variables. Accordingly, Boolean algebra is very useful in the design of electronic logic circuits. A useful way of displaying the results of a Boolean operation is with a truth table.
In logic (combinational) circuits, it is desirable to reduce the number of logic gates where possible both from the standpoint of cost and size. The present invention involves a method for determining constant pins in a combinational circuit. The method comprises the steps of associating an input of a combinational circuit with a first variable and a second variable, wherein said second variable is the complement of said first variable, computing for a first logical cell interconnected to said input a first mathematical representation, wherein said first mathematical representation is a function of the operation of said first logical cell and a function of said first value, computing for said first logical cell a second mathematical representation, wherein said second mathematical representation is a function of the operation of said first logical cell and a function of said second value, determining whether one of said first and second mathematical representations is equal to zero. Once constant pins are determined, it is generally possible to simplify the circuit.